下表是74HC138译码器的功能表.
请用基础门电路实现该译码器电路，用Verilog将电路描述出来。基础门电路包括：非门、多输入与门、多输入或门。
74HC138特有3个使能输入端：两个低有效（E1和E2）和一个高有效（E3）。除非E1和E2置低且E3置高，否则74HC138将保持所有输出为高。
根据真值表，写出逻辑表达式。 即可：
Y0_n = ~(E·(~A2)·(~A1)·(~A0));
Y1_n = ~(E·(~A2)·(~A1)·(A0));
Y2_n = ~(E·(~A2)·(A1)·(~A0));
Y3_n = ~(E·(~A2)·(A1)·(A0));
Y4_n = ~(E·(A2)·(~A1)·(~A0));
Y5_n = ~(E·(A2)·(~A1)·(A0));
Y6_n = ~(E·(A2)·(A1)·(~A0));
Y7_n = ~(E·(A2)·(A1)·(A0));
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
input A0 ,
input A1 ,
input A2 ,
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
);
wire E;
assign E = E3 & ~E1_n & ~E2_n;
assign Y0_n = ~(E & ~A2 & ~A1 & ~A0);
assign Y1_n = ~(E & ~A2 & ~A1 & A0);
assign Y2_n = ~(E & ~A2 & A1 & ~A0);
assign Y3_n = ~(E & ~A2 & A1 & A0);
assign Y4_n = ~(E & A2 & ~A1 & ~A0);
assign Y5_n = ~(E & A2 & ~A1 & A0);
assign Y6_n = ~(E & A2 & A1 & ~A0);
assign Y7_n = ~(E & A2 & A1 & A0);
endmodule
module DDC3_8(a,b,c,out)
input a;
input b;
input c;
output reg [7:0]out;
always@(a,b,c)
case({a,b,c})
3'b000: out = 8'b0000_0001;
3'b001: out = 8'b0000_0010;
3'b010: out = 8'b0000_0100;
3'b011: out = 8'b0000_1000;
3'b100: out = 8'b0001_0000;
3'b101: out = 8'b0010_0000;
3'b110: out = 8'b0100_0000;
3'b111: out = 8'b1000_0000;
endcase
38 译码器 case语句实现 ：
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
input A0 ,
input A1 ,
input A2 ,
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
);
reg Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r;
always@(*)
begin
casez({E3, E2_n, E1_n, A2, A1, A0})
6'b?1?_???: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
6'b??1_???: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
6'b0??_???: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
6'b100_000: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0111_1111;
6'b100_001: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1011_1111;
6'b100_010: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1101_1111;
6'b100_011: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1110_1111;
6'b100_100: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_0111;
6'b100_101: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1011;
6'b100_110: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1101;
6'b100_111: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1110;
default: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1111_1111;
endcase
end
assign {Y0_n, Y1_n, Y2_n, Y3_n, Y4_n, Y5_n, Y6_n, Y7_n} = {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r};
endmodule
全减法
38译码器和逻辑门实现全减器。 A为被减数，B为减数。Ci为低位的借位，D是差。Co是向高位的借位。
3-8译码器代码如下，可将参考代码添加并例化到本题答案中。
38译码器
module decoder_38(
input E;
input A0;
input A1;
input A2;
output reg Y0n;
output reg Y1n;
output reg Y2n;
output reg Y3n;
output reg Y4n;
output reg Y5n;
output reg Y6n;
output reg Y7n,
)
always@(*)
if(!E) begin
Y0n=1'b1;
Y1n=1'b1;
Y2n=1'b1;
Y3n=1'b1;
Y4n=1'b1;
Y5n=1'b1;
Y6n=1'b1;
Y7n=1'b1;
end
else
case({A3,A2,A1})
3'b000: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1111_1110;
3'b001: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1111_1110;
3'b010: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1111_1011;
3'b011: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1111_0111;
3'b100: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1110_1111;
3'b101: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1101_1111;
3'b110: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b1011_1111;
3'b111: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b0111_1111;
default:
3'b111: {Y7n,Y6n,Y5n,Y4n,Y3n,Y2n,Y1n,Y0n} = 8'b0111_1111;
endcase
分析 Ci为低位借位，算输出时候需要减去。 当被减数小于减数时候需要向高位借位。 输出借位co为1.
真值表为：
真值表求逻辑表达式方法
第一步：从真值表内找输出端为“1”的各行,把每行的输入变量写成乘积形式;遇到“0”的输入变量上加非号。
第二步：把各乘积项相加,即得逻辑函数的
则根据真值表可得到逻辑表达式为：
38译码器逻辑表达式为：
结合38译码器的表达式可以得到，
也就是将减数B、被减数A和借位Ci分别连接到到3-8译码器的A0、A1和A2，然后对输出Yin取反求和就可以得到全减器的输出。
思路： 先写出被减数和减数 以及输出的真值表，输入三位。 写出输出根据输入的逻辑表达式。 根据38译码器的逻辑表达式。 写出全减法输出对于38译码器输出的表达式。。。例化三八译码器，根据38译码器的输出信号，得到全减法输出信号表达式。wire [7:0] Y;
module decoder_38(
input E ,
input A0 ,
input A1 ,
input A2 ,
output reg Y0n ,
output reg Y1n ,
output reg Y2n ,
output reg Y3n ,
output reg Y4n ,
output reg Y5n ,
output reg Y6n ,
output reg Y7n
);
always @(*)begin
if(!E)begin
Y0n = 1'b1;
Y1n = 1'b1;
Y2n = 1'b1;
Y3n = 1'b1;
Y4n = 1'b1;
Y5n = 1'b1;
Y6n = 1'b1;
Y7n = 1'b1;
end
else begin
case({A2,A1,A0})
3'b000 : begin
Y0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
end
3'b001 : begin
Y0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
end
3'b010 : begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
end
3'b011 : begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
end
3'b100 : begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
end
3'b101 : begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1;
end
3'b110 : begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1;
end
3'b111 : begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0;
end
default: begin
Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1;
Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
end
endcase
end
end
endmodule
module decoder1(
input A ,
input B ,
input Ci ,
output wire D ,
output wire Co
);
wire [7:0] Y;
assign D = ~Y[1] + ~Y[2] + ~Y[4] + ~Y[7];
assign Co = ~Y[1] + ~Y[4] + ~Y[5] + ~Y[7];
decoder_38 decoder_38_inst(
.E (1) ,
.A0 (B) ,
.A1 (A) ,
.A2 (Ci) ,
.Y0n(Y[0]) ,
.Y1n(Y[1]) ,
.Y2n(Y[2]) ,
.Y3n(Y[3]) ,
.Y4n(Y[4]) ,
.Y5n(Y[5]) ,
.Y6n(Y[6]) ,
.Y7n(Y[7])
);
endmodule
```
