| hdmi | hdl-util | 472 | github.com/hdl-util/hd… | Send video/audio over HDMI on an FPGA |
| nontrivial-mips | trivialmips | 394 | github.com/trivialmips… | NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux. |
| axi | pulp-platform | 198 | github.com/pulp-platfo… | AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication |
| SystemVerilogReference | VerificationExcellence | 188 | github.com/Verificatio… | training labs and examples |
| logic | tymonx | 136 | github.com/tymonx/logi… | CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs. |
| verilog-mode | veripool | 113 | github.com/veripool/ve… | Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org. |
| sv-tests | SymbiFlow | 92 | github.com/SymbiFlow/s… | Test suite designed to check compliance with the SystemVerilog standard. |
| common_cells | pulp-platform | 73 | github.com/pulp-platfo… | Common SystemVerilog components |
| fx68k | ijor | 71 | github.com/ijor/fx68k | FX68K 68000 cycle accurate SystemVerilog core |
| USTC-RVSoC | WangXuan95 | 66 | github.com/WangXuan95/… | FPGA-based RISC-V CPU+SoC. |
| TrivialMIPS | trivialmips | 61 | github.com/trivialmips… | MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support |
| Deep-Neural-Network-Hardware-Accelerator | StefanSredojevic | 52 | github.com/StefanSredo… | SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software |
| svaunit | amiq-consulting | 49 | github.com/amiq-consul… | SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA) |
| SystemVerilogAssertions | VerificationExcellence | 47 | github.com/Verificatio… | Examples and reference for System Verilog Assertions |
| tvip-axi | taichi-ishitani | 47 | github.com/taichi-ishi… | AMBA AXI VIP |
| systemverilog.io | subbdue | 46 | github.com/subbdue/sys… | Code used in |
| AHB2 | GodelMachine | 43 | github.com/GodelMachin… | AMBA AHB 2.0 VIP in SystemVerilog UVM |
| SystemVerilogSHA256 | unixb0y | 37 | github.com/unixb0y/Sys… | SHA256 in (System-) Verilog / Open Source FPGA Miner |
| tnoc | taichi-ishitani | 37 | github.com/taichi-ishi… | Network on Chip Implementation written in SytemVerilog |
| FPGA-Application-Development-and-Simulation | loykylewong | 36 | github.com/loykylewong… | 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS). |
| gateware | swetland | 33 | github.com/swetland/ga… | A collection of little open source FPGA hobby projects |
| FTDI-245fifo-interface | WangXuan95 | 32 | github.com/WangXuan95/… | FPGA-based USB fast communication using FT232H/FT600 chip. |
| riscv-vip | jerralph | 29 | github.com/jerralph/ri… | For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug |
| fpga-virtual-console | Harry-Chen | 29 | github.com/Harry-Chen/… | VT220-compatible console on Cyclone IV EP4CE55F23I7 |
| FM_Radio | pbing | 28 | github.com/pbing/FM_Ra… | Simple mono FM Radio. |
| combinator-uvm | doswellf | 27 | github.com/doswellf/co… | UVM Testbench For SystemVerilog Combinator Implementation |
| amiq_apb | amiq-consulting | 26 | github.com/amiq-consul… | SystemVerilog VIP for AMBA APB protocol |
| aes128-hdl | mbgh | 25 | github.com/mbgh/aes128… | A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process. |
| virtio | tymonx | 23 | github.com/tymonx/virt… | Virtio implementation in SystemVerilog |
| AES | cjdrake | 22 | github.com/cjdrake/AES | Advanced Encryption Standard (AES) SystemVerilog Core |
| fpga-hash-table | johan92 | 21 | github.com/johan92/fpg… | Simple hash table on Verilog (SystemVerilog) |
| systemverilog-design-patterns | tenthousandfailures | 21 | github.com/tenthousand… | None |
| NoCRouter | agalimberti | 20 | github.com/agalimberti… | RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni |
| custom_uvm_report_server | kaushalmodi | 18 | github.com/kaushalmodi… | Customized UVM Report Server |
| verilog-sid-mos6581 | thomask77 | 17 | github.com/thomask77/v… | MOS6581 SID chip emulator in SystemVerilog |
| sv-1800-2012 | gvekony | 17 | github.com/gvekony/sv-… | IEEE Std 1800™-2012: IEEE Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language syntax definition for VS Code |
| svx | mxg | 16 | github.com/mxg/svx | SystemVerilog Extension Library – a library of utilities for generic programming and increased productivity |
| verilog-format | jiegec | 16 | github.com/jiegec/veri… | A naive verilog/systemverilog formatter |
| system-verilog-patterns | luuvish | 15 | github.com/luuvish/sys… | SystemVerilog Design Patterns |
| sv_image | nelsoncsc | 15 | github.com/nelsoncsc/s… | Reusable image processing modules in SystemVerilog |
| CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2 | karthisugumar | 15 | github.com/karthisugum… | A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator |
| nanoFOX | Dmitriy0111 | 14 | github.com/Dmitriy0111… | A small RISC-V core (SystemVerilog) |
| FPGA-SDcard-Reader | WangXuan95 | 14 | github.com/WangXuan95/… | FPGA-based SDcard Reader via SD bus. |
| uvm_debug | uvmdebug | 13 | github.com/uvmdebug/uv… | UVM interactive debug library |
| jtag_dpi | pulp-platform | 12 | github.com/pulp-platfo… | JTAG DPI module for SystemVerilog RTL simulations |
| sms | celesteneary | 12 | github.com/celestenear… | Sega Master System in SystemVerilog |
| nim-systemverilog-dpic | kaushalmodi | 11 | github.com/kaushalmodi… | Using Nim to interface with SystemVerilog test benches via DPI-C |
| svreal | sgherbst | 11 | github.com/sgherbst/sv… | Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats |
| axi_node | pulp-platform | 10 | github.com/pulp-platfo… | AXI X-Bar |
| Cryptography-in-Systemverilog | zhouchuanrui | 10 | github.com/zhouchuanru… | A collection of cryptographic algorthms implemented in SystemVerilog |
| axi4-interface | mmxsrup | 10 | github.com/mmxsrup/axi… | AXI4 and AXI4-Lite interface definitions |
| SHIT-Core-NSCSCC2020 | Superscalar-HIT-Core | 10 | github.com/Superscalar… | a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog |
| ahb3lite_pkg | RoaLogic | 9 | github.com/RoaLogic/ah… | Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces |
| sv_csv_parser | Mochenx | 9 | github.com/Mochenx/sv_… | A CSV file parser, written in SystemVerilog |
| jarvisuk | shady831213 | 9 | github.com/shady831213… | Just A Really Very Impressive Systemverilog UVM Kit |
| freecellera-uvm | Freecellera | 8 | github.com/Freecellera… | Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org) |
| Verilog-FixedPoint | WangXuan95 | 8 | github.com/WangXuan95/… | Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. |
| common_verification | pulp-platform | 7 | github.com/pulp-platfo… | SystemVerilog modules and classes commonly used for verification |
| reflection | tudortimi | 7 | github.com/tudortimi/r… | Reflection API for SystemVerilog |
| vpi | tudortimi | 7 | github.com/tudortimi/v… | SystemVerilog wrapper over the Verilog Programming Interface (VPI) |
| YasaUvk | zhajio1988 | 7 | github.com/zhajio1988/… | 🐛UVM verification kits which uses YASA as simulation script |
| dragonphy2 | StanfordVLSI | 7 | github.com/StanfordVLS… | Open Source PHY v2 |
| NN_Network_On_Chip | eanchlia | 7 | github.com/eanchlia/NN… | Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to interface four instances of neural engine with AHB bus to create NOC. |
| constraintlayering | tenthousandfailures | 6 | github.com/tenthousand… | SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples |
| tbcm | taichi-ishitani | 6 | github.com/taichi-ishi… | Basic Common Modules |
| FPGA-SDcard-Reader-SPI | WangXuan95 | 6 | github.com/WangXuan95/… | FPGA-based SDcard Reader via SPI. |
| SystemVerilog | yuxuanZh | 5 | github.com/yuxuanZh/Sy… | This is a code repo for previous projects in Digital Design & Verification |
| AHB-SystemVerilog | forever-gk | 5 | github.com/forever-gk/… | None |
| yamm | amiq-consulting | 5 | github.com/amiq-consul… | YAMM package repository |
| Gaia | GeraltShi | 5 | github.com/GeraltShi/G… | Generate UVM testbench framework template files with Python 3 |
| SV-for-Design | jomonkjoy | 5 | github.com/jomonkjoy/S… | Systemverilog Design Packages |
| usb20dev | esynr3z | 5 | github.com/esynr3z/usb… | USB 2.0 FS Device controller IP core written in SystemVerilog |
| gpio_agent | imokanj | 5 | github.com/imokanj/gpi… | General Purpose I/O agent written in UVM |
| Fake-SDcard | WangXuan95 | 5 | github.com/WangXuan95/… | Imitate SDcard using FPGAs. |
| LLAPI | Kitrinx | 5 | github.com/Kitrinx/LLA… | Bliss-Box Low Latency API Implementation in SystemVerilog |
| entc_missing_semester | abarajithan11 | 5 | github.com/abarajithan… | An initiative to familiarize the students of ENTC with tools (Vivado…) and languages (SystemVerilog…) |
| aes128 | smartfoxdata | 5 | github.com/smartfoxdat… | The aes128 is a SystemVerilog implementation of the AES algorithm with 128-bit key |
| SonyCellSPU | ppujari24 | 5 | github.com/ppujari24/S… | Implementation of a Dual Issue Pipelined Multimedia Processor Architecture (SONY Cell SPU) in SystemVerilog |
| sva_traces | go2uvm | 5 | github.com/go2uvm/sva_… | Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors |
| SystemVerilog_TB | scott7950 | 4 | github.com/scott7950/S… | SystemVerilog Testbench |
| System-Snake | andrewandrepowell | 4 | github.com/andrewandre… | Snake game implemented in SystemVerilog, running on the Digilent Nexys DDR 4. |
| Single-Cycle-Processor | tianrenz2 | 4 | github.com/tianrenz2/S… | Single-Cycle RISC-V Processor in systemverylog |
| Digital-piano-in-SystemVerilog | z-e-r-0 | 4 | github.com/z-e-r-0/Dig… | This project is compatible for BASYS3 and Beti Board. It has 4 modules (incuding top module). |
| HDL-Safe | arokasprz100 | 4 | github.com/arokasprz10… | Simple safe lock mechanism written in SystemVerilog. |
| crc_calc | hellgate202 | 4 | github.com/hellgate202… | Simple and effective parallel CRC calculator written in synthesizable SystemVerilog |
| riscv_asm_sv | jeras | 4 | github.com/jeras/riscv… | RISC-V assembler/dis-assembler written in SystemVerilog |
| svlint-action | dalance | 4 | github.com/dalance/svl… | None |
| tue | taichi-ishitani | 4 | github.com/taichi-ishi… | Useful UVM extensions |
| uvmgen | edcote | 4 | github.com/edcote/uvmg… | UVM verification component and testbench generator tool |
| fpga-projects | alisemi | 4 | github.com/alisemi/fpg… | FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders. |
| cagt | amiq-consulting | 4 | github.com/amiq-consul… | Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast an UVM based agent for any protocol. |
| tvip-apb | taichi-ishitani | 4 | github.com/taichi-ishi… | Verification IP for AMBA APB Protocol |
| Hard-JPEG-LS | WangXuan95 | 4 | github.com/WangXuan95/… | FPGA-based JPEG-LS image encoder in near-lossless mode. |
| systemverilog | zstechly | 3 | github.com/zstechly/sy… | System Verilog Presentation / example code I wrote to use as a template for future test benches |
| Memory | chenyangbing | 3 | github.com/chenyangbin… | None |
| FPGA-Fighting-Game | seanluo1 | 3 | github.com/seanluo1/FP… | I created a two-player fighting game that can be played on an Altera Cyclone IV FPGA. |
| Async_FIFO_Verification | akzare | 3 | github.com/akzare/Asyn… | Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM. |
| sv_practice | harpreetbhatia | 3 | github.com/harpreetbha… | Practice exercises for SystemVerilog, UVM … |
| digital_circuits | anthonyabeo | 3 | github.com/anthonyabeo… | A collection of digital logic circuits |
| HDL | embeddedmoscow | 3 | github.com/embeddedmos… | Verilog & SystemVerilog examples for articles |
