| tvip-axi | taichi-ishitani | 47 | github.com/taichi-ishi… | AMBA AXI VIP |
| AHB2 | GodelMachine | 43 | github.com/GodelMachin… | AMBA AHB 2.0 VIP in SystemVerilog UVM |
| riscv-vip | jerralph | 29 | github.com/jerralph/ri… | For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug |
| amiq_apb | amiq-consulting | 26 | github.com/amiq-consul… | SystemVerilog VIP for AMBA APB protocol |
| amba3-vip | luuvish | 19 | github.com/luuvish/amb… | amba3 apb/axi vip |
| AMBA_APB_SRAM | courageheart | 16 | github.com/couragehear… | AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP). |
| yuu_ahb | seabeam | 7 | github.com/seabeam/yuu… | UVM AHB VIP |
| yuu_apb | seabeam | 5 | github.com/seabeam/yuu… | UVM APB VIP, part of AMBA3&AMBA4 feature supported |
| ahb2apb_bridge_vip | designsolver | 4 | github.com/designsolve… | AHB to APB Bridge VIP |
| tvip-apb | taichi-ishitani | 4 | github.com/taichi-ishi… | Verification IP for AMBA APB Protocol |
| yuu_vip_gen | seabeam | 3 | github.com/seabeam/yuu… | UVM VIP architecture generator |
| axi4_vip | muneebullashariff | 1 | github.com/muneebullas… | Verification IP for APB protocol |
| i2c_vip | muneebullashariff | 1 | github.com/muneebullas… | Verification IP for I2C protocol |
| VIP | RuijieDV | 1 | github.com/RuijieDV/VI… | 通用VIP |
| axi_vip | nsdeo12 | 1 | github.com/nsdeo12/axi… | Axi VIP |
| apb_vip | asveske | 1 | github.com/asveske/apb… | APB VIP (UVM) |
| spi-vip | mcagriaksoy | 1 | github.com/mcagriaksoy… | None |
| simple-spi-vip | mcagriaksoy | 1 | github.com/mcagriaksoy… | None |
| jtag_vip_uvm | emmanouil-komninos | 1 | github.com/emmanouil-k… | None |
| spi_vip | muneebullashariff | 0 | github.com/muneebullas… | Verification IP for SPI protocol |
| apb_vip | muneebullashariff | 0 | github.com/muneebullas… | Verification IP for APB protocol |
| git_i2c_master | davidchen6 | 0 | github.com/davidchen6/… | i2c_master_vip |
| UART_VIP | kammulchandani | 0 | github.com/kammulchand… | UART VIP Project |
| vip_clock | ottohorvath | 0 | github.com/ottohorvath… | UVM based clock generator VIP |
| axi_vip | aunics | 0 | github.com/aunics/axi_… | UVM SV based axi vip |
| SV_VIP | CelvinSXll | 0 | github.com/CelvinSXll/… | SV VIP supported by UVM |
| vip_edaplaygrnd | emmanouil-komninos | 0 | github.com/emmanouil-k… | None |
| dummy_vip | pulp-training | 0 | github.com/pulp-traini… | Files for the IP Integration Exercise |
| tvip | taichi-ishitani | 0 | github.com/taichi-ishi… | None |
| RAM_VIP | NikolaF-95 | 0 | github.com/NikolaF-95/… | UVM VIP for Single Port RAM Synchronous Read/Write |
| vip_reset | ottohorvath | 0 | github.com/ottohorvath… | A simple basic reset VIP based on UVM 1.1d. |
| uart_vip | muneebullashariff | 0 | github.com/muneebullas… | Verification IP for UART protocol |
| AxiVIP | nguyenquanicd | 0 | github.com/nguyenquani… | An AxiVIP supports both master and slave mode |
| FIFO_VIP | kammulchandani | 0 | github.com/kammulchand… | None |
| uvm.vip | PhilOls | 0 | github.com/PhilOls/uvm… | None |
| axis_image_vip | hchsiao | 0 | github.com/hchsiao/axi… | None |
| spi_uvm_vip | me-sachinsingh | 0 | github.com/me-sachinsi… | None |
| spi_vip_uvm | Alexnorvag | 0 | github.com/Alexnorvag/… | None |
| APB3_SLAVE_VIP | ManojMJ5 | 0 | github.com/ManojMJ5/AP… | None |
| 1G-PCS-VIP | egorman44 | 0 | github.com/egorman44/1… | UVM component that could be used in your Verification environment |
| AXI-VIP-Development | AniketBadhan | 0 | github.com/AniketBadha… | None |
| APB_VIP_Repo | Dankumar | 0 | github.com/Dankumar/AP… | None |
| AHB5 | aunics | 0 | github.com/aunics/AHB5 | AMBA AHB 5.0 VIP in SystemVerilog based on UVM |
| accessor_class_example | amiq-consulting | 0 | github.com/amiq-consul… | An example of using accessor classes and parameterization to reduce the number of VIP instances |
