| uvmprimer | raysalemi | 174 | github.com/raysalemi/u… | Contains the code examples from The UVM Primer Book sorted by chapters. |
| logic | tymonx | 136 | github.com/tymonx/logi… | CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs. |
| UVMReference | VerificationExcellence | 110 | github.com/Verificatio… | Reference examples and short projects using UVM Methodology |
| uvm-tutorial-for-candy-lovers | cluelogic | 79 | github.com/cluelogic/u… | Source code repo for UVM Tutorial for Candy Lovers |
| svaunit | amiq-consulting | 49 | github.com/amiq-consul… | SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA) |
| tvip-axi | taichi-ishitani | 47 | github.com/taichi-ishi… | AMBA AXI VIP |
| AHB2 | GodelMachine | 43 | github.com/GodelMachin… | AMBA AHB 2.0 VIP in SystemVerilog UVM |
| uvm_agents | dovstamler | 41 | github.com/dovstamler/… | UVM agents |
| UVM | mayurkubavat | 38 | github.com/mayurkubava… | UVM examples and projects |
| tnoc | taichi-ishitani | 37 | github.com/taichi-ishi… | Network on Chip Implementation written in SytemVerilog |
| combinator-uvm | doswellf | 27 | github.com/doswellf/co… | UVM Testbench For SystemVerilog Combinator Implementation |
| axi-uvm | marcoz001 | 23 | github.com/marcoz001/a… | yet another AXI testbench repo. 😉 This is for my UVM practice. marcoz001.github.io/axi-uvm/ |
| custom_uvm_report_server | kaushalmodi | 18 | github.com/kaushalmodi… | Customized UVM Report Server |
| uvm-utest | nosnhojn | 17 | github.com/nosnhojn/uv… | None |
| AMBA_APB_SRAM | courageheart | 16 | github.com/couragehear… | AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP). |
| ISP_UVM | nelsoncsc | 15 | github.com/nelsoncsc/I… | A Framework for Design and Verification of Image Processing Applications using UVM |
| second_edition | advanced-uvm | 15 | github.com/advanced-uv… | Code for the second edition of Advanced UVM. |
| uvm_debug | uvmdebug | 13 | github.com/uvmdebug/uv… | UVM interactive debug library |
| easyUVM | nelsoncsc | 13 | github.com/nelsoncsc/e… | A simple UVM example with DPI |
| UVM | chiggs | 12 | github.com/chiggs/UVM | Mirror of the Universal Verification Methodology from sourceforge |
| uvm_apb | smartfoxdata | 12 | github.com/smartfoxdat… | uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol |
| uvm_gen | hjking | 11 | github.com/hjking/uvm_… | UVM Generator |
| uvm-components | pulp-platform | 11 | github.com/pulp-platfo… | Contains commonly used UVM components (agents, environments and tests). |
| uvm_candy_lover | zhajio1988 | 10 | github.com/zhajio1988/… | 🍬UVM candy lover testbench which uses YASA as simulation script |
| ref-uvm-i2c-wb | ic7x24 | 10 | github.com/ic7x24/ref-… | None |
| jarvisuk | shady831213 | 9 | github.com/shady831213… | Just A Really Very Impressive Systemverilog UVM Kit |
| freecellera-uvm | Freecellera | 8 | github.com/Freecellera… | Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org) |
| RISC_VERIF_DEMO_0 | MushroomZQ | 8 | github.com/MushroomZQ/… | a very simple risc_cpu verification demo with uvm |
| uvm_reg_to_ipxact | amiq-consulting | 8 | github.com/amiq-consul… | None |
| uvm_axi | smartfoxdata | 8 | github.com/smartfoxdat… | uvm_axi is a uvm package for modeling and verifying AXI protocol |
| uvm_axi4lite | smartfoxdata | 8 | github.com/smartfoxdat… | uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol |
| uvm | accellera | 7 | github.com/accellera/u… | None |
| ahb3_uvm_tb | designsolver | 7 | github.com/designsolve… | AMBA 3 AHB UVM TB |
| yuu_ahb | seabeam | 7 | github.com/seabeam/yuu… | UVM AHB VIP |
| uvm_starter | smartfoxdata | 7 | github.com/smartfoxdat… | uvm_starter is a simple template for starting uvm projects |
| YasaUvk | zhajio1988 | 7 | github.com/zhajio1988/… | 🐛UVM verification kits which uses YASA as simulation script |
| AHB-APB_Bridge_UVM_Env | Gateway91 | 6 | github.com/Gateway91/A… | AHB-APB UVM Verification Environment |
| UVM-APB_RAL | JoseIuri | 5 | github.com/JoseIuri/UV… | This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT. |
| yamm | amiq-consulting | 5 | github.com/amiq-consul… | YAMM package repository |
| Gaia | GeraltShi | 5 | github.com/GeraltShi/G… | Generate UVM testbench framework template files with Python 3 |
| gpio_agent | imokanj | 5 | github.com/imokanj/gpi… | General Purpose I/O agent written in UVM |
| UART | darthsider | 5 | github.com/darthsider/… | UART design in SV and verification using UVM and SV |
| uvm_sin_cos_table | vlotnik | 5 | github.com/vlotnik/uvm… | Contains source code for sin/cos table verification using UVM |
| UVM-Verification-Testbench-For-SimpleBus | rdou | 5 | github.com/rdou/UVM-Ve… | None |
| yuu_apb | seabeam | 5 | github.com/seabeam/yuu… | UVM APB VIP, part of AMBA3&AMBA4 feature supported |
| regModel | briandong | 5 | github.com/briandong/r… | This script builds the UVM register model, based on pre-defined address map in markdown (mk) style |
| sva_traces | go2uvm | 5 | github.com/go2uvm/sva_… | Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors |
| uvm_agent_gen | blargony | 4 | github.com/blargony/uv… | UVM Agent Generator |
| i2c_wb_sv_uvm | rajkumarraval | 4 | github.com/rajkumarrav… | None |
| UVM-Simulation-JTAG | serinvarghese | 4 | github.com/serinvarghe… | UVM Simulation Model for a JTAG Interface |
| UvmEnvUartApb | nguyenquanicd | 4 | github.com/nguyenquani… | This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetigating the UVM env. |
| tue | taichi-ishitani | 4 | github.com/taichi-ishi… | Useful UVM extensions |
| uvmgen | edcote | 4 | github.com/edcote/uvmg… | UVM verification component and testbench generator tool |
| cagt | amiq-consulting | 4 | github.com/amiq-consul… | Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast an UVM based agent for any protocol. |
| UVM_Verification | avashist003 | 4 | github.com/avashist003… | Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence |
| tvip-apb | taichi-ishitani | 4 | github.com/taichi-ishi… | Verification IP for AMBA APB Protocol |
| uvm_auto | mingzhang952 | 3 | github.com/mingzhang95… | uvm auto generator |
| uart2bustestbench | hanysalah | 3 | github.com/hanysalah/u… | UVM Verification IP to uart2bus IP. |
| uvm-phase-jumping | PedroHSCavalcante | 3 | github.com/PedroHSCava… | Simple UVM phase jumping |
| UVM-Verification-Testbench-For-FIFO | rdou | 3 | github.com/rdou/UVM-Ve… | A complete UVM verification testbench for FIFO |
| uvm | kippy620 | 3 | github.com/kippy620/uv… | Learning uvm step by step. |
| Async_FIFO_Verification | akzare | 3 | github.com/akzare/Asyn… | Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM. |
| uvmBasics | adibis | 3 | github.com/adibis/uvmB… | Basics of UVM via an APB slave |
| yuu_vip_gen | seabeam | 3 | github.com/seabeam/yuu… | UVM VIP architecture generator |
| UVM_primer | hmomkar | 3 | github.com/hmomkar/UVM… | Contains UVM example from Ray salemi authored book |
| sv_practice | harpreetbhatia | 3 | github.com/harpreetbha… | Practice exercises for SystemVerilog, UVM … |
| RISCV-UVM-Verification | vatsal184 | 3 | github.com/vatsal184/R… | None |
| A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM | alice820621 | 3 | github.com/alice820621… | A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which slave to choose. Subsequently four monitors and scoreboards record each slave’s test results. |
| async_FIFO | dadongshangu | 3 | github.com/dadongshang… | This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming’s paper and the UVM is coded by me(Xianghzi Meng) |
| wishbone_uvc | alexzhang007 | 3 | github.com/alexzhang00… | Wishbone protocol open source universal verification component (UVC). It is easy to be used in UVM verification environment for opencpu. |
| yuu_clock | seabeam | 3 | github.com/seabeam/yuu… | UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available |
| uvm | aravindprakash | 2 | github.com/aravindprak… | UVM Examples |
| uvm | SymbiFlow | 2 | github.com/SymbiFlow/u… | None |
| UVM_Python_UVMC | JoseIuri | 2 | github.com/JoseIuri/UV… | This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor®. |
| MAC_BFM | jchengX | 2 | github.com/jchengX/MAC… | wifi |
| uvm_lab | chenfengrugao | 2 | github.com/chenfengrug… | a pratical uvm lab |
| uvm_testbench | mowsong | 2 | github.com/mowsong/uvm… | SoC Verification with UVM |
| UVM_UART_Example | WeiChungWu | 2 | github.com/WeiChungWu/… | An UVM example of UART |
| apb_uvm | chan-henry | 2 | github.com/chan-henry/… | Advanced Peripheral Bus (APB) UVM testbench project |
| uvm-templates | nbrummel | 2 | github.com/nbrummel/uv… | This repo provides uvm templates to start a sv uvm project. |
| UVM_verification | ganesh-ps | 2 | github.com/ganesh-ps/U… | None |
| SimpleAdder-UVM | tamannarupani | 2 | github.com/tamannarupa… | A simple adder implementation and verification using UVM 1.2 |
| uvm-indirect-registers | uwesimm | 2 | github.com/uwesimm/uvm… | an infrastructure to implement arbitrary indirect registers on top of uvm |
| ExtremeDV_UVM | zhajio1988 | 2 | github.com/zhajio1988/… | UVM resource from github, run simulation use YASAsim flow |
| MPSoC-DV | PacoReinaCampo | 2 | github.com/PacoReinaCa… | MPSoC verified with UVM/OSVVM/FV |
| cpu | kruegz | 2 | github.com/kruegz/cpu | CPU design with SystemVerilog/UVM verification |
| UVM-Verification-Testbench-For-APB | rdou | 2 | github.com/rdou/UVM-Ve… | None |
| UVM-Testbench-for-Flex-Timer | hrishikeshpujari | 2 | github.com/hrishikeshp… | None |
| UART-16550 | Shivanagender123 | 2 | github.com/Shivanagend… | This is UVM testbench for UART with multiple test cases. |
| SoC-DV | PacoReinaCampo | 2 | github.com/PacoReinaCa… | System on Chip verified with UVM/OSVVM/FV |
| AHB_APB-Bridge | Shivanagender123 | 2 | github.com/Shivanagend… | This is normal basic UVM testbench for AMBA Bridge AHB_APB |
| Shift_Register | Shivanagender123 | 2 | github.com/Shivanagend… | This is normal basic UVM testbench for shift register with reference model using queues in scoreboard and RTL |
| uvm | akilystic | 1 | github.com/akilystic/u… | None |
| UVM | tyxuanyuanlx | 1 | github.com/tyxuanyuanl… | None |
| AHB-with-FIFO | Emi-Pushpam | 1 | github.com/Emi-Pushpam… | UVM methodology |
| basic_uvmc_oct | nelsoncsc | 1 | github.com/nelsoncsc/b… | A simple UVM testbench using UVM Connect and Octave |
| uvm_ahb_lite | zhelnio | 1 | github.com/zhelnio/uvm… | uvm ahb lite environment |
| SMC_Verification | fifthheaven | 1 | github.com/fifthheaven… | verify SMC via UVM |
| uvm_objections | dcblack | 1 | github.com/dcblack/uvm… | UVM Objection performance |
| uvm_uart_apb_env | nguyensinhton9x | 1 | github.com/nguyensinht… | uvm_ver_3 |
