xilinx fpga opencl加速RTL Kernel Examples

SDAccel_Examples/getting_started/rtl_kernel/ ---- github

//top
///
// Description: This is a wrapper of module "krnl_vadd_rtl_int"
///

// default_nettype of none prevents implicit wire declaration.
`default_nettype none
`timescale 1 ns / 1 ps 

module krnl_vadd_rtl #( 
  parameter integer  C_S_AXI_CONTROL_DATA_WIDTH = 32,
  parameter integer  C_S_AXI_CONTROL_ADDR_WIDTH =