SystemVerilog中package import和`include方式的差异 --这个文章的解释更好
SystemVerilog Coding Guidelines: Package import versus include
To explain in simple terms,
- we use import for importing a package. Using import you can select components of a package like a class or a task or “*” to import complete package.
- we use include to physically place the code of a file while compiling. With include, you just get entire code here but cannot have part of the include file.
SystemVerilog中的package提供了保存和共享数据、参数和方法的机制，可以在多个module、class、program和interface中重用。
package中声明的内容都属于这个package作用域（scope）。在使用这些内容时，需要先import这个package，然后通过package引用。
SystemVerilog中的package通过package和endpackage声明
