uvm register model

uvm register model

• 1. uvm register model 要点
• • Reference

1. uvm register model 要点

• 可以在reference model中发起reg的read/write操作
• 可以在sequence中发起这个操作，reference model/sequence都是调用register model的 read/write操作，
• 不论是在reference model还是sequence中，都是通过句柄访问register model
• register model一般在base_test中定义；
• 然后通过句柄传到env的reference model中；
• sequence中调用register model 可以通过先把句柄传入seuqncer中，然后通过p_sequencer访问
• sequence中调用register model 也可以通过uvm_config_db 的方法把register model 传进来；
  class bus_base_seq extends uvm_sequence #(pcie_cpl_item);

class bus_base_seq extends uvm_sequence #(pcie_cpl_item);
  `uvm_object_utils(bus_base_seq)
  `uvm_declare_p_sequencer(pcie_cpl_sequencer)
 
  global_pkt_config my_pkt_config;
  // Register model:
  reg_top_block reg_rm;
  pcie_cpl_item rsp;
  // Properties used by the various register access methods:
  rand uvm_reg_data_t data; // For passing data
  uvm_status_e status;      // Returning access status
  
  function new(string name = "bus_base_seq");
    super.new(name);
  endfunction

  // Getting a handle to the register model
  task body;
  //uvm_config_db  得到register model
    if(!uvm_config_db #(reg_top_block)::get(null, get_full_name(), "reg_top_block", reg_rm)) begin
      `uvm_error("body", "Could not find reg_top_block")
    end
endclass

在env或者在base_test中set
uvm_config_db #(reg_top_block)::set(this, "*", "reg_top_block", reg_rm);

Reference

1. [UVM]图解UVM寄存器訪問方法（Register Access Methods）.
2. uvm设计分析——reg