assertion for reset synchronous release

Code

   sequence mark_time(sig,realtime t);
      @(posedge sig) (1,t=$realtime);
   endsequence

   property p_rstn_sync(en,rstn,clk);
      realtime t1,t2;
      @(posedge clk) disable iff (!en) mark_time(rstn,t1) ##0 mark_time(clk,t2) |-> if(t1!=t2) (1,$display("rstn_sync FAIL!, sync_release time:%t",t1));
   endproperty

   a_rstn_sync: assert property (p_rstn_sync(1,rstn,clk));

The property p_rstn_sync compare the realtime of (posedge clk) and (posedge rstn).

en: enable assertion
rstn:asserted reset signal
clk:asserted clock signal

Example Wave

1. At posedge clk, rstn synchronous release. the events of (posedge clk) and (posedge rstn) happend at the same time 30.0ns.
   
2. Report Fail. (posedge rstn) delay 10ps to (posedge clk).
   .