Chapter 10-11-12 Digital Design, Inveter, Static Logic Gates

fun4analog
139 阅读2分钟

Chapter 10 Models for Digital Design

Digital MOSFET Model

数字把MOS看成一个带电容和电阻的开关管

MOS电阻工作在深度线性区, 量级在几K ohm级别

电容就是Cgs, Cds, Cgd

Delay Time

tdelay=0.7RCt_{delay}=0.7RC

Rise/Fall time

trise=2.2RCt_{rise}=2.2RC

The MOSFET Pass Gate

NMOS 擅长传低电平 GND, bad at passing VDD, (Output会变成 VDD-Vthn)

PMOS 擅长传高电平 VDD, bad at passing 0 (Output 会变成Vthp)

所以把NMOS并联PMOS就形成了Transmission Gate, 这样高低电平都可以传输了!

Measurement

Using a piece of coax to probe would add 110pF capacitance and 1Mohm to ground at the point we probe!

Chapter 11 The Inverter

The inverter 可算最简单的模拟和数字电路了

DC Characteristic

Switching point, 翻转点PMOS电流=NMOS电流

Vsp=βnβpVthn+(VDD−Vthp)1+βnβpV_{sp}=\frac{\sqrt{\frac{\beta_n}{\beta_p}}V_{thn}+(VDD-V_{thp})}{1+\sqrt{\frac{\beta_n}{\beta_p}}}

因为NMOS的\mu_n是PMOS的3倍, 为了让反转点在1/2VDD, PMOS的W/L是NMOS的3倍

Switching Characteristic

inverter就是电阻和电容并联 因此, rise time tPLH fall time tPHL = 0.7R_{out}C_{in}

The ring Oscillator

fos=1n(tPHL+tPLH)f_{os}=\frac{1}{n(t_{PHL}+t_{PLH})}

n 是奇数

Dynamic Power Dissipation of the inverter is

Pavg=Ctot⋅VDD2⋅fclkP_{avg}=C_{tot}\cdot VDD^2\cdot f_{clk}

Layout of the Inverter

需要防止inverter latch up, 也就是寄生三极管开启, 导致PMOS和NMOS always on

解决方法: 在PMOS和NMOS之间多打Contact, 降低VDD到GND的阻抗, 预防latchup

多级buffer驱动

为了减小延迟, 最优化的N级数是

N=lnCloadCinN=ln\frac{C_{load}}{C_{in}}

每一级增益为

A=[CloadCin]1NA=[\frac{C_{load}}{Cin}]^\frac{1}{N}

但实际电路一般达不到, 有个3-4级就差不多了

Other Inverter Configuration

NMOS -Only Output Driver

NMOS supper buffer

当In=0时, M1和M4 off, M3和M2 on, Out= 0

当In=VDD时, M1和M4 on, Out=VDD-Vthn (这时候M3 on, M2 off, M3 use large L/W 管子)

当然更好的办法是有额外的charge pump能提高M4的gate

Inverter with Tri-State Outputs

可以用Inverter + Transmission Gate

Chapter 12 Static Logic Gates

DC Characteristics of the NAND and NOR gates

对于NAND NMOS串联减半, PMOS并联加倍

Transconductace ratio of NAND gate=βn4βp\text{Transconductace ratio of NAND gate}=\frac{\beta_n}{4\beta_p}

对于NOR NMOS并联加倍, PMOS串联减半

Transconductace ratio of NOR gate=4βnβp\text{Transconductace ratio of NOR gate}=\frac{4\beta_n}{\beta_p}

Layout:

NOR or NAND can share a drain area or source area

Switching Characteristic

For NAND, quick estimate of the delay:

Vout从高到低的delay, 是经历了N个resistor Rn

tPHL=0.7NRnCloadt_{PHL}=0.7NR_nC_{load}

Vout从低到高的delay, 只需要一个PMOS on就行了

tPLH=0.7RpCloadt_{PLH}=0.7R_pC_{load}

Complex CMOS Logic Gates

And-Or-Inverter (AOI) 可以利用布尔函数化简, 化简成Invert形式, 再利用NAND 或者 NOR的形式叠加到一起, 而且只需要做一半比如NMOS端的逻辑, PMOS做成对偶就行了

avatar
文章
阅读
粉丝