Chapter 3 The Metal Layers

Passivation layer: 在芯片顶端第一层的insulator

Overglass layer: 在insulator上的开窗, 也喜欢叫PAD

Capacitance of Metal-to-Substrate:

C_{pad->sub}=areaC_{plate}+perimeterC_{fringe}

金属上留过大电流会造成electromigration (metal physically moves) 这也是为什么做PMIC需要做EM仿真检查, Check Javg and Jmax, 确保不会烧毁

Contact or Via

Via: 电阻 Estimate 10ohm/contact. 电流: no more than 100uA of current flow per via

最后介绍了MIM and MOM金属层电容

MIM capacitor (Metal-Insulator-Metal): 电容值小, 而且金属-衬底的寄生电容较大

MOM capacitor (Metal-Oxide-Metal): 电容值更大一些, 目前在先进工艺更常用

Chapter 4 The Active and Poly Layers

In a layout we can simply count the number of times poly crosses active to count the number of MOSFET in the layout. Poly跨过active area的次数就代表有多少根MOSFET

The FinFET

A thin (fixed width) fin of silicon is surrounded by a gate, generally implement using metal rather than poly, to provide control of the channels on three sides.

The Poly Wire

为了减少poly sheet resistance 可加入silicide (金半混合物)

隔离active area的叫field regions (FOX), also called Shallow Trench Isolation (STI)

In practice, substrate connections are used wherever possible 多打P-SUB的Contact!

Chapter 5 Resistor, Capactors, MOSFETs

Resistors

R(T)=R(T_{0})(1+TCR1(T-T_{0}))

TCR1 first-order temperature coefficient

In general, temp co of resistor is positive, 即温度上升电阻上升, 因为载流子的mobilities下降更厉害

但是也不排除有negative temp co的电阻, 实际中还得看PDK文件

Voltage Coefficient

A typical value of VCR1 is 8000 ppm/V

一些提高resistor匹配的layout技巧:

Using Unit Elements
Guard Rings (Place P+ implant, the substrate contact removes the injected carries and holds the substrate, ideadly, at a fixed potential (ground).)
Interdigitated Layout 插指状
Common-Centroid Layout 中心对称
Dummy Elements

Capacitors

Parasitic: 最大寄生电容就是poly1 to substrate (bottom plate parasitic capacitance)

MOSFE Ts

Lateral Diffusion: Leffctive = Ldrawn - 2Ldiff

Poly跨过active area的次数就代表有多少根MOSFET

Cgs=CGSO*W

Cgd = CGDO*W

Chapter 3,4,5 Metal, Active and Poly Layers, Resistor, Capactors,MOSFETs