Verilog HDLBits 刷题记录

Getting Started

0x01.Geting Started

Q: Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

A:

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

说明:

1.RTL 指逻辑电路图

2.连续赋值语句（assign）,用于对wire型变量进行赋值

0x02.Output Zero

Q: Build a circuit with no inputs and one output that outputs a constant 0 Now that you've worked through the previous problem, let's see if you can do a simple problem without the hints.

A: 模仿上一题的代码,此处要求输出zero变量恒为1

module top_module( output zero);
    assign zero = 0;
endmodule

说明:

注意赋值语句后面有分号 module语句后面也有分号 模块代码块声明结束后需要使用endmodule

Verilog Language

Basics

0x01.Simple wire

Q: Create a module with one input and one output that behaves like a wire.

A: 即要求有一个输入，一个输出

扒取一下HDLBits网站的图:

module top_module(input in, output out);
    assign out = in;
endmodule

说明：

assgin为连续赋值语句，

0x02.Four wires

Q: Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

a -> w

b -> x

b -> y

c -> z

The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. From outside the module, there are three input ports and four output ports.

A: wire类型的赋值语句,可以理解为烧电路板时在两个端口连接导线

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
endmodule

or 

module top_module(
    input a,b,c,
    output w,x,y,z );
    assign w = a;
    assign {x, y} = {b, b};
    assign z = c;
endmodule

说明： assign x = y = b;在HDLBits测试环境下报错

正确且更为nice的语法为: assign {x, y} = {b, b};

0x03.Four wires

Q:Create a module that implements a NOT gate.

写一个非门,将wire信号进行取反

A: 取反的Verilog语法是 ! or ~

module top_module(input in, output out)
    assign out = ~in;
endmodule

or

module top_module(input in, output out)
    assign out = !in;
endmodule

0x04.AND gate

Q:Create a module that implements an AND gate.

This circuit now has three wires (a, b, and out). Wires a and b already have values driven onto them by the input ports. But wire out currently is not driven by anything. Write an assign statement that drives out with the AND of signals a and b.

A: 可以使用按位与(位运算)&来表示,也可以使用逻辑与(真值运算)&&来表示与门

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a&b;
endmodule

0x05.NOR gate

Q: Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

A: 或非门，或运算后取反

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a|b);
endmodule

0x06.XNOR gate

Q: Create a module that implements an XNOR gate.

A:

module top_module(
    input a,
    input b,
    output out);
    assign out = ((~a)&b)|(a&(~b));