今天做数字逻辑作业的时候这个题在写输出高阻态时出现了报错
一开始的代码：
library ieee;
use ieee.std_logic_1164.all;
entity register8 is
port (
clk: in std_logic;
ena: in std_logic;
d: in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0)
);
end register8;
architecture register74ls374 of register8 is
begin
process (clk, ena, d)
begin
if ena = '1' then
q <= "ZZZZZZZZ";
else
if clk'event and clk = '1' then
q <= d;
end if;
end if;
end process;
end register74ls374;
报错：
Error: Design requires 8 output enable signals, but the device can contain only 6 output enable signals
在网上搜到英特尔官方的解答：
| CAUSE: | The Fitter cannot fit the design in the device because it requires the specified number of global output enable signals, but the selected device can contain only the specified number of global output enable signals. These signals may have been implemented with global buffers or by turning on the Global Signal logic option. |
|---|---|
| ACTION: | Reduce the number of global signals in the design, or use array signals. You can also try removing GLOBAL primitives, turning off the Global Signal logic option, or directing the Fitter to select one or more automatic global signals with the Auto Global Clock logic option. |
用局部信号存高阻态再赋值给输出引脚即可：
library ieee;
use ieee.std_logic_1164.all;
entity register8 is
port (
clk: in std_logic;
ena: in std_logic;
d: in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0)
);
end register8;
architecture register74ls374 of register8 is
signal r: std_logic_vector(7 downto 0);
begin
process (clk, ena, d)
begin
if ena = '1' then
r <= "ZZZZZZZZ";
q <= r;
else
if clk'event and clk = '1' then
q <= d;
end if;
end if;
end process;
end register74ls374;
