SDK
下载MKL26对应SDK 下载链接
我选择了windows和keilIDE,下载后解压缩，里面文件目录为
- boards:包含用于FRDM-KL46开发板的demo样例
- CMSIS
- devices：包含,,
drivers:用于外设驱动utilities:一些功能函数arm:启动文件，在keil中也有提供，可以使用keil中pack管理器中的内容引入项目来替代cmsis-drivers
- docs:文档
- middleware
在线的api文档链接
Register accessor macros消失
对比发现在MKL26Z4.h中对于SIM_SCGC5_REG这类macro消失，在NXP论坛上查到类似链接，新版SDK中SIM_SCGC5需使用SIM->SCGC5进行引用。
对比新旧版本的MKL26Z4.h可以发现问题
新版本中定义了一个结构体，通过结构体可以索引对应寄存器
/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
__IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
uint8_t RESERVED_0[4092];
__IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[4];
__IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
__IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint8_t RESERVED_2[4];
__IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
uint8_t RESERVED_3[8];
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_4[12];
__IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
__IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
__IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
__IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
__IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
uint8_t RESERVED_5[4];
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint8_t RESERVED_6[4];
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
uint8_t RESERVED_7[156];
__IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
__O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
} SIM_Type;
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base address */
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
在旧版本中也有类似的结构体，但是额外定义了新的变量索引寄存器
/** SIM - Peripheral register structure */
typedef struct SIM_MemMap {
uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
uint8_t RESERVED_0[4092];
uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[4];
uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint8_t RESERVED_2[4];
uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
uint8_t RESERVED_3[8];
uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_4[12];
uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
uint8_t RESERVED_5[4];
uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint8_t RESERVED_6[4];
uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
uint8_t RESERVED_7[156];
uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
} volatile *SIM_MemMapPtr;
/* SIM - Register instance definitions */
/* SIM */
#define SIM_SOPT1 SIM_SOPT1_REG(SIM_BASE_PTR)
#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM_BASE_PTR)
#define SIM_SOPT2 SIM_SOPT2_REG(SIM_BASE_PTR)
#define SIM_SOPT4 SIM_SOPT4_REG(SIM_BASE_PTR)
#define SIM_SOPT5 SIM_SOPT5_REG(SIM_BASE_PTR)
#define SIM_SOPT7 SIM_SOPT7_REG(SIM_BASE_PTR)
#define SIM_SDID SIM_SDID_REG(SIM_BASE_PTR)
#define SIM_SCGC4 SIM_SCGC4_REG(SIM_BASE_PTR)
#define SIM_SCGC5 SIM_SCGC5_REG(SIM_BASE_PTR)
#define SIM_SCGC6 SIM_SCGC6_REG(SIM_BASE_PTR)
#define SIM_SCGC7 SIM_SCGC7_REG(SIM_BASE_PTR)
#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM_BASE_PTR)
#define SIM_FCFG1 SIM_FCFG1_REG(SIM_BASE_PTR)
#define SIM_FCFG2 SIM_FCFG2_REG(SIM_BASE_PTR)
#define SIM_UIDMH SIM_UIDMH_REG(SIM_BASE_PTR)
#define SIM_UIDML SIM_UIDML_REG(SIM_BASE_PTR)
#define SIM_UIDL SIM_UIDL_REG(SIM_BASE_PTR)
#define SIM_COPC SIM_COPC_REG(SIM_BASE_PTR)
#define SIM_SRVCOP SIM_SRVCOP_REG(SIM_BASE_PTR)
类似的对于PORTC_PCR0同样需要修改，因此以前的代码为
SIM_SCGC5|=0x0800; //通过逻辑”或”置 1，单独使能 PORTC 时钟
PORTC_PCR0=0x0100;//设置 PTC0 为 GPIO
PORTC_PCR4=0x0100;//设置 PTC4 为 GPIO
GPIOC_PDDR =0x0011;//配置 PTC0、PTC4 为输出
GPIOC_PDOR=0x0011; //输出 PTC0、PTC4 为 1，小灯点亮
需要改为
SIM->SCGC5|=0x0800; //通过逻辑”或”置 1，单独使能 PORTC 时钟
PORTC->PCR[0]=0x0100;//设置 PTC0 为 GPIO
PORTC->PCR[4]=0x0100;//设置 PTC4 为 GPIO
GPIOC->PDDR =0x0011;//配置 PTC0、PTC4 为输出
GPIOC->PDOR =0x0011; //输出 PTC0、PTC4 为 1，小灯点亮
预定义
在keil中的编译器c++部分define加入CPU_MKL26Z256VLH4,使得fsl_device_registers.h中的预定义生效
Undefined symbol ImageZI$$Limit (referred from startup_mkl26z4.o).
microlib
在Target选项卡中选择Use MicroLIB.microlib
