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教程地址链接
NVIDIA Jetson TX2 J21 Header Pinout
SPI on Jetson – Using Jetson-IO
nvidia jetson_GPIO : A Python library that enables the use of Jetson's GPIOs 注：（自己的文件安装路径）
sudo cp /usr/local/lib/python3.5/dist-packages//Jetson/GPIO/99-gpio.rules /etc/udev/rules.d/
Nvidia Jetson tx2 操作GPIO 需要在sudo模式下运行
如果import Jetson.GPIO as GPIO时报错no module named Jetson ,使用sudo运行python即可import成功
NVIDIA Developer Forums
GPIO doesn`t work?
This should be such a simple task, but I can’t get GPIO to work on my TX2. I’ve noticed that the mappings seem to have been moved to start at 256 instead of 0 (as it was on X1), but even adding 256 to the GPIO number, I can’t seem to toggle GPIO.
I’ve tried PZ0 (200+256), PK2 (82+256), PK3 (83+256), PBB3 (219+256), and others, and none of them toggle when commanded. I’m using a typical sysfs workflow, but the pins simply don’t change.
root@tegra-ubuntu:/sys/class/gpio# echo 475 > export
root@tegra-ubuntu:/sys/class/gpio# cd gpio475
root@tegra-ubuntu:/sys/class/gpio/gpio475# cat direction
in
root@tegra-ubuntu:/sys/class/gpio/gpio475# echo out > direction
root@tegra-ubuntu:/sys/class/gpio/gpio475# cat direction
out
root@tegra-ubuntu:/sys/class/gpio/gpio475# cat value
0
root@tegra-ubuntu:/sys/class/gpio/gpio475# echo 1 > value
root@tegra-ubuntu:/sys/class/gpio/gpio475# cat value
1
Everything works as expected there, but the levels don’t change on the pins.
Hi T186 gpio pin maps is kind different with t210, there’re to group like below and you can reference to the …/kernel/kernel-4.4/include/dt-bindings/gpio/tegra186-gpio.h to figure out the gpio number.
GPIOs 256-319, platform/c2f0000.gpio, tegra-gpio-aon: GPIOs 320-511, platform/2200000.gpio, tegra-gpio:
/* GPIOs implemented by main GPIO controller */
#define TEGRA_MAIN_GPIO_PORT_A 0
#define TEGRA_MAIN_GPIO_PORT_B 1
#define TEGRA_MAIN_GPIO_PORT_C 2
#define TEGRA_MAIN_GPIO_PORT_D 3
#define TEGRA_MAIN_GPIO_PORT_E 4
#define TEGRA_MAIN_GPIO_PORT_F 5
#define TEGRA_MAIN_GPIO_PORT_G 6
#define TEGRA_MAIN_GPIO_PORT_H 7
#define TEGRA_MAIN_GPIO_PORT_I 8
#define TEGRA_MAIN_GPIO_PORT_J 9
#define TEGRA_MAIN_GPIO_PORT_K 10
#define TEGRA_MAIN_GPIO_PORT_L 11
#define TEGRA_MAIN_GPIO_PORT_M 12
#define TEGRA_MAIN_GPIO_PORT_N 13
#define TEGRA_MAIN_GPIO_PORT_O 14
#define TEGRA_MAIN_GPIO_PORT_P 15
#define TEGRA_MAIN_GPIO_PORT_Q 16
#define TEGRA_MAIN_GPIO_PORT_R 17
#define TEGRA_MAIN_GPIO_PORT_T 18
#define TEGRA_MAIN_GPIO_PORT_X 19
#define TEGRA_MAIN_GPIO_PORT_Y 20
#define TEGRA_MAIN_GPIO_PORT_BB 21
#define TEGRA_MAIN_GPIO_PORT_CC 22
#define TEGRA_MAIN_GPIO_PORT_DD 23
#define TEGRA_MAIN_GPIO(port, offset) \
((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
/* GPIOs implemented by AON GPIO controller */
#define TEGRA_AON_GPIO_PORT_S 0
#define TEGRA_AON_GPIO_PORT_U 1
#define TEGRA_AON_GPIO_PORT_V 2
#define TEGRA_AON_GPIO_PORT_W 3
#define TEGRA_AON_GPIO_PORT_Z 4
#define TEGRA_AON_GPIO_PORT_AA 5
#define TEGRA_AON_GPIO_PORT_EE 6
#define TEGRA_AON_GPIO_PORT_FF 7
#define TEGRA_AON_GPIO(port, offset) \
((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
