makefile是make所依赖的指令文件

假设有一个C项目，项目结构如下图所示

- proj
  - src/
  - incl/
  - bin/
  - lib/

执行的shell命令如下所示：

	gcc -I${HOME}/incl -c hello.c
	gcc -o hello hello.o
	rm -f hello.o
	mv hello ${HOME}/bin

借助makefile组织命令

#隐含规则
INCL=-I${HOME}/incl

.SUFFIXES: .cpp .c
.cpp.o:
	g++ ${INCL} -c $<

.c.o:
	gcc ${INCL} -c $<

#C++编译
hellocpp:hellocpp.o
	echo "开始编译"
	g++ -o hellocpp hellocpp.o
	rm -f hellocpp.o
	mv hellocpp ${HOME}/bin
	echo "编译结束"

#C编译
hello:hello.o
	echo "开始编译"
	gcc -o hello hello.o
	rm -f hello.o
	mv hello ${HOME}/bin
	echo "编译结束"

或者如下所示

#最后形成的Makefile
INCL=-I${HOME}/incl
BIN=$(HOME)/bin
OBJ1=hellocpp.o
OBJ2=hello.o

.SUFFIXES: .cpp .c
.cpp.o:
	g++ ${INCL} -c $<

.c.o:
	gcc ${INCL} -c $<

all: hellocpp hello

#C++编译
hellocpp:${OBJ1}
	@echo "============开始编译============"
	g++ -o $@ $?
	@rm -f ${OBJ1}
	@mv $@ ${BIN}
	@echo "============编译结束============"
	@echo ""

#C编译
hello:${OBJ2}
	@echo "============开始编译============"
	gcc -o $@ $?
	@rm -f ${OBJ2}
	@mv $@ ${BIN}
	@echo "============编译结束============"
	@echo ""

引用

【1】知乎