This is a new series of posts for craft an LLVM Backend for LCC architecture for tutorial purpose. (LCC stands for Low Cost Computer)
The LCC is a simple but powerful architecture from <C and C++ Under the Hood>. An instruction set architecture not only contains the instruction set but also the way how to store, fetch, execute the program composed by those instructions, including Calling Convention etc, which mostly will be described in LLVM target description files (.td).
The instruction execution procedure of LCC is described as following quotion.
1. Loads PC register with the entry point of program.
2. Fetch the instruction the PC register points to. That is, the CPU loads the IR register with the instruction in the memory cell whose address is in the PC register. The CPU does not remove the instruction from its memory cell. Instead, it makes a copy of it. Thus, the contents of the memory cell that the PC register points to are unaffected.
3. Increment the PC register.
4. Execute the instruction in the IR.
5. Go back to step 2 until halt.
A program must has an entry point to let the CPU knows where is its first instruction to be executed, which is the offset relative to the beginning of program file. And the OS will load a program at an address in memory, that address is called load point, then let the PC points to the program's entry point by a branch instruction. In addition, during the program loading, the OS will do more things before branch to program's entry point, such as runtime linking etc.
The following image is the structure of LCC. It has 8 general purpose registers started from r0 to r7 with assignments of r5, r6, r7 for special use as frame pointer register if frame pointer is used, as stack pointer register if stack is used, and as link return register as subroutine call is used. And it has pc register to contain the address for next instruction to be executed, ir (instruction register) register to store the current executed instruction, and 4 1-bit flag registers to store the status of ALU.
Moreover, each register except the flag registers and memory cell are 16 bits. That means the word size in LCC is 16 bits, and its memory is word addressable. Totally, its has 2 to the 16 (65536) cells in its memory array. And its stack grows down.
The instructions it supports are the following:
This is the architecture we are going to make an LLVM backend for.
The steps for this series of post will follow the similar tutorial, Tutorial: Creating an LLVM Backend for the Cpu0 Architecture.
Actully, it bases on Cpu0 Architecture tutorial, but for LCC architecture. To see what is difference to be modified to make a new backend for different architecutre. And to comprehend the LLVM backend structure.
To begin with, we can follow the steps of LLVM Target Registration Minimal Setup to setup our LCC target. Then we will craft the target description files, then fill in the needed backend classes etc, in later posts. Stay tuned.
