##Variable Setting.
set NETLIST
set SDC
set LIB
set TOP
read_verilog $NETLIST
current_design $TOP
source $LIB
link
read_sdc $SDC
update_timing
##For register & memory check
set outFileName $TOP
set all_mem_cell [filter_collection [get_cells -hier -quiet *] {@is_memory cell==true}]
set register_pin_tmp [all_registers -clock_pin]
set REG_DETAIL_REPORT false
set_propagated_clock [all_clocks]
set_operating_conditions -analysis_type on_chip_variation
set FILE1 [format "%s" ${outFileName}_clk_register_detail_pin.rpt]
set FILE2 [format "%s" ${outFileName}_clk_register_mem_summary.rpt ]
set FILE3 [format "%s" ${outFileName}_clk_register_detail_cell.rpt]
set FILE4 [format "%s" ${outFileName}_clk_mem_detail_pin.rpt]
set FILE5 [format "%s" ${outFileName}_clk_mem_detail_cell.rpt]
set FILE6 [format "%s"${outFileName}_unconstrained_register_memory.rpt]
echo "==================================================================" > $FILE2 echo "CLOCK WAVEFORM INFORMATION" >> FILE2 echo "==================================================================" >> \FILE2 echo "CLK_NAME PERIOD WAVEFORM" >> $FILE2
