Table of Contents
1 Basic Steps for Writing an LLVM Backend
- Minial setup for Target Registration
- TargetMachine and Target Registration
- Register Info
- Instruction Info
- XXXISelDAGToDAG.cpp, XXXISelLowering.cpp for Instruction Selection
- AsmPrinter TargetAsmInfo
- TargetSubtarget for -mcpu=xxx and -mattr=xxx commandline options (Optional)
2 LLVM Backend Initializations
| locations | names |
|---|---|
| RISCV/RISCVAsmPrinter.cpp:207 | LLVMInitializeRISCVAsmPrinter() |
| RISCV/AsmParser/RISCVAsmParser.cpp:2449 | LLVMInitializeRISCVAsmParser() |
| RISCV/RISCVTargetMachine.cpp:35 | LLVMInitializeRISCVTarget() |
| RISCV/Disassembler/RISCVDisassembler.cpp:54 | LLVMInitializeRISCVDisassembler() |
| RISCV/TargetInfo/RISCVTargetInfo.cpp:23 | LLVMInitializeRISCVTargetInfo() |
| RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp:140 | LLVMInitializeRISCVTargetMC() |
2.1 XXXAsmPrinter()
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
}
2.2 XXXAsmParser()
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmParser() {
RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target());
RegisterMCAsmParser<RISCVAsmParser> Y(getTheRISCV64Target());
}
2.3 XXXTarget()
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
auto PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR);
initializeRISCVExpandPseudoPass(*PR);
}
2.4 XXXDisassembler()
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
// Register the disassembler for each target.
TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
createRISCVDisassembler);
TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
createRISCVDisassembler);
}
2.5 XXXTargetInfo()
Target &llvm::getTheRISCV32Target() {
static Target TheRISCV32Target;
return TheRISCV32Target;
}
Target &llvm::getTheRISCV64Target() {
static Target TheRISCV64Target;
return TheRISCV64Target;
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() {
RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
"32-bit RISC-V", "RISCV");
RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
"64-bit RISC-V", "RISCV");
}
2.6 XXXTargetMC()
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
TargetRegistry::RegisterObjectTargetStreamer(*T, createRISCVObjectTargetStreamer);
TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
// Register the asm target streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T, createRISCVNullTargetStreamer);
}
}
